Help judge what defects are for this amendment being allowable

Started by Weng Tianxiang, 04-09-17 at 11:11 PM

Previous topic - Next topic

Weng Tianxiang

Hi,
The lessons learned from many professional lawyers and Examiners from this website make amending my second pending amendment much easier, more reliable and more satisfactory, at least from my point of view.

Here are the lessons I have learned for an inventive method:
1. If claim 1 is allowable, all its dependent claims are allowable.

2. Concentrate attentions to words of claim 1. All arguments for claim 1 must be closely related to its wording.

3. Use most effective ways to defend your limitations on claim 1.

4. Do not add applicant's subjective judgment to affect Examiner's mind, but by reasoning.

Here is claim 1 of my second pending amendment responsive to a non-final Office action after first RCE. The last Office action rejects 16 of 24 claims and remaining 8 claims are allowable if all their parent limitations are accumulated.

Any comments are welcome.

Claim 1:
A method for use in coding a source code in HDL for an integrated circuit of wave-pipelining, the method comprising:

a)   coding a first code component in HDL, HDL being selected from a group of VHDL, Verilog and SystemVerilog, and the first code component being synthesized to generate a first logic block of the integrated circuit;

b)   coding a second code component in HDL, the second code component being interconnected with the first code component, and the second code component being synthesized to generate a second logic block of the integrated circuit; and

c)   coding one of a plurality of concurrent link statements, the link statement identifying both the first code component and the second code component, and the link statement triggering a synthesis tool to generate the circuit as the integrated circuit of wave-pipelining instead of a normal pipeline circuit.

Underlined text in red in step c) is added this time to emphasize the special coding structure.

Why claim 1 is non-obvious
McElvain at [0006] does disclose the code structure of claim 1: coding a circuit may comprise coding two code components and an interconnection to link the code components, but the code structure cannot be obviously expanded to include coding a wave-pipelined circuit. Here are reasons:

a)   It is a well-known fact that a wave-pipelined circuit is far superior over a pipeline circuit of the same function in respect of speed, silicon area and power consumption. Generally speaking, a normal pipeline circuit of a function appeases before a wave-pipelined circuit of the same function. For all applications a designer's first task is to design a circuit which is workable; after that an improvement in respect of speed, silicon area and power consumption may be needed. For a normal pipeline circuit to be improved, the circuit is to become a wave-pipelined circuit of the same function.

b)   Any code structures for a circuit can be generated as a normal pipeline circuit if the circuit needs more than one clock cycle to finish its function, but the code for a circuit with the same function must have a special code structure, two code components and a link statement interconnecting them, to be successfully generated as a wave-pipelined circuit by a synthesis tool based on what this invention teaches. In other words, the specific code structure for a wave-pipelined circuit is not obvious for a person with ordinary skill in the art to figure out.

c)   Current HDL standard lacks semantics to instruct a synthesis tool to generate a set of code to be a wave-pipelined circuit. In other words there are no ways for a synthesis tool to generate a wave-pipelined circuit under current HDL.

d)   A plurality of concurrent link statements is invented to concentrate all sufficient and necessary information to help a synthesis tool to finish its job. And the newly invented link statement is part of the specific code structure.

2)   Burnette has nothing to do with the present invention. ...

As for claims 2 to 24:
Dependent claims 2 to 24 are allowable at least for the same reasons as claim 1.


All amendment comments are very short and limited within one page.

Please help judge:
1. If there is any defect for the words of claiming 1.

2. What is the possibility for this amendment to be allowable.

Thank you.

Weng

Weng Tianxiang

Hi still_learnin,

Your guess is perfect right that I am amazing at:
"some Examiners will treat the phrase beginning with "to" (to prevent data contamination from ...) as intended use, and ignore the rest of the phrase following "to."

In the interview the Examiner did mention that the phrase: "to prevent data contamination from ...) as intended use.


Quoteif so, you might rewrite as something like:
Quote
synthesizing the first code component ... to produce logic that prevents data contamination from occurring on any of one or more critical paths of the integrated circuit;

I immediate responded the Examiner with the word you added in blue color, but she said that she is not interested in the logic, but in how the present invention does to prevent data contamination from occurring.

What I said is that how to prevent data contamination from occurring is not subject of the present invention, the application has nothing to do with the how and that is what the application asks a synthesis tool to deal with.

Finally she asked me on how a link statement identifies 2 code components. I help her to find the support from the specification. During the process, I found 2 very important concepts not used in the claim 1.

Final version of my claim 1 for supplemental amendment is as follows:

Claim 1 (currently amended)
A method for use in synthesizing a source code in Hardware Description Language (HDL, hereafter) for an integrated circuit of wave-pipelining, the method comprising:

a)   scanning for a concurrent link statement of a plurality of types, the concurrent link statement identifying a first code component critical path component and a second code component wave-pipelining component in HDL for the integrated circuit, and HDL being selected from a group [[of]] comprising VHDL, Verilog and SystemVerilog;

b)   synthesizing the first code component critical path component, in combination with synthesizing a first part of the second code component wave-pipelining component if the first part comprises a sole output register, to produce logic that prevents data contamination from occurring on any of one or more critical paths of the integrated circuit; and

c)   synthesizing the second code component wave-pipelining component.

It seems to me that the interview results are very satisfying:
1. I did explained that how to prevent data contamination from occurring is not my subject matter and has nothing to with the application. She seems to be unsatisfying with it.

2. Under her guidance I made amendments: from first code component to critical path component and from second code component to wave-pipelining component.

After the change she might think to give allowance.

And she asked me to send supplemental amendment within 1 day that, of cause, I will follow.

The interview lasted 2 hour!

Before the interview the Examiner asked to do interviews for both pending applications and each would be given half a hour. Finally almost all 2 hours were focused on one application.

After the interview now I clearly know what the Examiner is thinking about!

A very important and valuable lesson!

Weng





www.intelproplaw.com

Terms of Use
Feel free to contact us:
Sorry, spam is killing us.

iKnight Technologies Inc.

www.intelproplaw.com